Manav Goyal

C A O - Others

Introduction and Overview of Computer Architecture

  • Introduction to Computer Systems
  • Overview of Organization and Architecture
  • Functional Components of a Computer
  • Registers and Register Files
  • Interconnection of Components
  • Organization of the Von-Neumann Machine and Harvard Architecture
  • Performance of Processor

Data Representation and Computer Arithmetic

  • Fixed Point representation of Numbers
  • Algorithms for Arithmetic Operations -=> Multiplication
    • Booths
    • Modified Booths
  • Algorithms for Arithmetic Operations -=> Division
    • Restoring -=> To Multiply Unsigned numbers
      • Left Shift
      • Subtraction
      • Carry Control Bit
    • Non-Restoring
  • Floating Point representation with IEEE standards and Algorithms for common Arithmetic Operations
    • Data Type
      • Fixed Point
      • Floating Point
      1. Mantissa
      2. Base
      3. Exponent
    • Steps
      • Convert Decimal to Binary
      • Normalize the Number
      • N = Mantissa, E = Exponent
    • Representation of Nonnumeric Data
      • Character codes

Fundamentals of Computer Architecture

  • Introduction to ISA -=> Instruction Set Architecture
  • Instruction formats
  • Instruction types and addressing modes
  • Instruction execution -=> Phases of instruction cycle
  • Assembly language programming
  • Subroutine call and return mechanisms
  • Single cycle Data path design
  • Introduction to multi cycle data path
  • Multi cycle Instruction execution
  • CISC & RISC

Memory System Organization and Architecture

  • Memory Systems Hierarchy

  • Main Memory Organization

    • Main Memory -=> Physical Address = Block Number + Block Offset/ Size
    • Physical Memory > Blocks > Words/ Block Size > Word Length (Byte)

  • Types of Main Memory

    • Memory interleaving and its characteristics and performance

  • Cache Memories

    • Cache Hit -=> Required Block/Word is present in Cache
    • Cache Miss -=> Required Block/Word is not present in Cache
    • Conflict Miss -=> Cache Miss dur to not utilizing available space
    • Line Size (Cache Indexing) = Block Size (MM Indexing)
    • Mapping -=> Types based on way of Stored data -=> Get Data from Address generated by CPU
        1. Direct Map -=> Block Number % Number of Lines -=> Position of Blocks is fixed even if there is other space
        • Physical Address for MM (Generated by CPU) = Block no. + Block Offset/Size
        • Physical Address for Cache = Tag + Line Number + Block Offset/Size
        • Searching is very easy (Only 1 comparison)
        1. Fully Associative -=> Block can be anywhere
        • Physical Address = Tag/Block no. + Block Offset
        • Hit ratio increases, No. of comparisons also increases
        1. K-way Set Associative -=> Block No. % No. of Set -=> Can be in any Line of the Set
        • No. of Set (n) = No. of Lines / K
        • Physical Address for MM (Generated by CPU) = Block no. + Block Offset/Size
        • Physical Address for Cache = Tag + Set no. + Block Offset/Size
    • Coherence
    • Locality of Reference -=> Tendency of processor to access the same Memory Block again
      • Spatial -=> Relative to Space
        • Close Proximity -=> Word adjacent to current word will be accessed next
        • Block Size -=> Keeping more Words in a Block increases Hit ratio
      • Temporal -=> Relative to Time
        • Current Word will be referenced again in the future
        • LRU is used
    • Replacement Algorithms -=> Replacing Data from Cache -=> Not used for Direct Mapping -=> To increase Hit ratio
      • FIFO
      • Least Recently Used (LRU) -=> Replace the one who came at first
      • Most recently used (MRU)
      • Random

  • Virtual Memory Systems

    • Paging
      • Logical Space = No. of Page + Page Offset/ Size
      • Physical Address = Frame No. + Frame Offset/ Size
      • No. of Entries in PT = No. of Pages
      • Size of PT = Page No. * Frame No.
    • Logical to Physical Address translation

  • Translation Lookaside Buffer (TLB) -=> Cache Memory -=> Stores Frame No.

    • Effective Memory Access Time = Hit(TLB + MM) + Miss(TLB + MM + MM)

  • Reliability of Memory Systems

  • Error

    • Error Type
      • Single Bit Error
      • Burst Error
    • Error Detecting
      • Simple Parity
      • 2D Parity Check
      • Check Sum
      • Cyclic Redundancy Check (CRC)
    • Error Correcting system
      • Hamming Code -=> 7 Bit = Data (4) + Parity (3) -=> Parity = 2n
      1. Calculation of total numbers of redundant bits
      2. Checking the position of the redundant bits
      3. Lastly, calculating the values of these redundant bits

Interfacing and Communication

  • I/O Fundamentals
    • Use of Interface -=> Speed, Signal, Format, Functionality
    • Handshaking
    • Buffering
  • I/O Techniques
    • Programmed I/O
    • Interrupt-driven I/O
    • Direct Memory Access (DMA)
  • Interrupt
    • Hardware
      • Maskable -=> Processor can't ignore
      • Non-Maskable
    • Software -=> Have higher priority
      • Vectored -=> Fixed location to go to when interrupts happen
      • Non-Vectored
  • Interrupt Methods
    • Daisy chaining in Priority
    • Parallel Priority
  • Interrupt overhead
  • Buses
    • Syn
  • Chronous and asynchronous
  • Arbitration

Device Subsystems

  • External storage systems
  • Organization and structure of disk drives
    • Electronic- magnetic and optical technologies
  • RAID Levels
  • I/O Performance

Performance Enhancements

  • Classification of models
  • Flynns taxonomy of parallel machine models ( SISD, SIMD, MISD, MIMD)
  • Pipelining -=> Process of arrangement of Hardware to increase overall performance by Overlapping
    • Instruction & Data Pipelining
    • Overlapping -=> Simultaneous execution of more than 1 process at a time
    • Load/Instructions
    • Clock Cycle -=> No. of Stages a instruction has to pass through
      • Total for non-pipelined (NP) = CC for 1 x No. of Instructions
      • Total for pipelined (P) = No. of Stages + (No. of Instructions - 1)
      • Clock per Instruction (CPI) ⋍ 1 -=> Execution of 1 process in each cycle
      • Speedup = NP/P
    • Stages
      • 4-stage -=> IF, ID, OF, Ex
      • 5-stage -=> IF, ID, Ex, MEM, WB
    • Interface Register/Latches -=> Stores intermideate results
    • Stage-time Diagram
      • Efficiency = Total box/Box used
    • Stage Delay
    • Pipelined data path
  • Hazards in Pipelining
    • Data
      • Read after Write (RAW) -=> True Dependency
        • Find Domain (Where data is read) & Range (Where data is stored) -=> Intersection of Range (I1) & Domain (I2) should by NULL
        • Solved by Operand Forwarding/Short Circuiting
      • Write after Read (WAR) -=> Anti Dependency
        • Find Domain & Range -=> Intersection of Domain (I1) & Range (I2) should by NULL
      • Write after Write (WAR) -=> Output Dependency
        • Find Domain & Range -=> Intersection of Range (I1) & Range (I2) should by NULL
        • Solved by Register Renaming -=> Values are stored temporarily in a Register
    • Structural -=> When multiple instructions need same resource
      • Resource Duplication
      • Resource Pipelining
      • Resource Rename
    • Control -=> Instructions who change the program counter leads
      • Stalling -=> Stopping and finding if there is Branch
  • Multiprocessor architecture
  • Overview of Shared Memory architecture
  • Distributed architecture
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