8086 Microprocessor - Microprocessor And Interfacing
- 8085 Architecture
- 8-bit processor size, 16-bit address bus, Can access up to 64 Kb
- Doesn't support Instruction queue, pipelined architecture and Multiprocessing
- Can address 28=256 I/O
- Low cost
- Only supports integer and decimal
- Memory space is not segmented
- 8086 Architecture
- Enhanced version of 8085 microprocessor designed by intel in 1976
- Powerful instruction set
- Operations Modes
- Max Mode
- It is a multiprocessor system
- Can handover the task to other component
- Min Mode
- It is a single-processor system
- Features
- It is a 40 Pin IC, 16-bit processor
- Its operating voltage is 5 Volt, Frequency is 5 Mega-Hertz
- Total memory addressing capacity is 1 Mb (External)
- 16-Bit data bus & 20-bit address bus
- Can address 216=65,536 I/O
- It has 14 16-Bit registers
- Higher throughput
- Microprocessor based system
- Basic
- These are electrical system

- Types
- System Hardware
- Discrete components -=> Microprocessor, Memory, I/O
- Components connected by bus -=> Address, Data, Control
- System Software
- Group of programs that monitors the function of entire system
- MPU communicate with Memory & I/O using System bus
- Address bus
- Unidirectional bus, Connected to memory and i/o
- Processor wants to know the address of external device (Not other way as there is only 1 processor)
- Data bus
- Bidirectional bus
- Transfers binary data and instructions
- Control lines
- It reads and writes timing signals
- Internal 8086 Architecture

- Divided into 2 independent functional units
- Bus interface unit
- Functions
- Fetch the instruction or data from memory
- Write the data to memory
- Write the data to ports
- Reads data from ports
- Functional Parts
- Instruction pointer (IP)
- It is a 16-bit register that keeps the address of memory location of coming instruction to be executed
- Segment register
- The memory space (1 Mb) is segmented into 4 blocks
- Each block specified by register with maximum size 64 Kb
- Code Segment (CS)
- Data Segment (CS)
- Stack Segment (CS)
- Extra Segment (CS)
- Instruction queue
- BIU performs its operations in parallel with execution unit
- BIU fetches instruction bytes while execution unit is executing operations
- The prefetched instruction is saved in group of high speed registers known as instruction queue
- Execution unit
- Functions
- To tell BIU where to fetch the instruction or data from
- To decode instruction
- To execute instruction
- Contains the control circuitry to perform various internal operations
- Functional Parts
- General purpose register (GPRs)
- 8086 processor consists of 4 GPR, Each of size 16-bit
- Can use each of these as 2 8-bit registers
- AH AL, BH BL, CH CL, DH DL
- Pointer & Indexed register
- Pointer
- Stack pointer
- Base pointer
- Indexed
- Source index
- Destination index
- ALU
- 16-bit, Performs arithmetic and logical operation 8-bit and as well as 16-bit
- Flag register
- 16-bit

- 7 flags unused, Remaining 9 flags are divided into 2 categories
- Status flag = 6
- Carry, Auxiliary, Zero, Sign, PArity, Overflow
- Control flag = 3
- Direction, Interrupt enable, Trap
- Timing & Control unit (CU)
- CU directs all internal operations and also responsible for generation of control signal
- Pin Diagram
- 40 pin (DIP)

- Physical Address of 8086
- Memory Segmentation
- Total memory size is divided into segments (area in memory) of various sizes
- Data is stored as bytes and each byte has some specific address
- 8086 has 20 lines address bus
- Memory can be addressed as 220 = 1 Mb
- Address ranging from 00000H to FFFFFH
- 8086 has 4 different types of segment -=> Each 16-bits, Each registers stores the base address (Starting address)
- Code Segment
- Data Segment
- Stack Segment
- Extra Segment
- Convert 16-bit into 20-bit
- BIU appends OH to LSB of address
- Effective Address = Starting + Offset